I. Field of the Invention
The present invention relates to an improvement of an echo canceler for eliminating an echo caused by an impedance mismatch in two-wire/four-wire conversion.
II. Description of the Prior Art
Active and extensive studies have been made for a variety of practical applications so as to provide an integrated services digital network (ISDN), thereby achieving a multipurpose digital network (for telephone and nontelephone communications), at low cost. For example, the development of two-wire bidirectional digital transmission using a subscriber's cable for transmitting an analog speech signal is one of the objectives in providing such an ISDN system.
An echo canceler is known as a means for realizing two-wire bidirectional digital transmission. For example, a conventional echo canceler is described in "Digital Echo Cancellation for Baseband Data Transmission", IEEE Transactions on Acoustics, Speech and Signal Processing Vol. ASSP-27, No. 6, PP 768-781, December 1979. A D/A (digital to analog) converter (DAC) of the conventional echo canceler of this type generally converts 12-bit data. In order to obtain an LSI (large scale integration) echo canceler, the number of bits of the D/A converter is preferably small.
Another conventional echo canceler with a single memory is described in "A New Digital Echo Canceler for Two-Wire Subscriber Lines", IEEE Transactions on Communications, Vol. COM-29, No. 11, pp 1573-1581, November 1981.
FIG. 1 is a block daigram of a conventional echo canceler. Referring to FIG. 1, reference numerals 1 and 2 denote input and output terminals, respectively; 3, a transmitter; 4, a receiver; 5, an adaptive digital filter (ADF); 6, a D/A converter (DAC); 7, a subtractor; 8, a sample-and-hold circuit (SH); 9, an A/D converter (ADC); 10, a low-pass filter (LPF); 11, a hybrid circuit (HYB); and 12, a two-wire transmission line. The circuit shown in FIG. 1 is connected to another echo canceler through the two-wire transmission line. If the two-wire line is regarded as a subscriber cable, one echo canceler is located at the subscriber station, whereas the other echo canceler is located at the local switching center. For the sake of simplicity, assume that baseband transmission is performed, and that the echo canceler shown is located at the subscriber station.
A transmitted signal from the subscriber terminal is supplied to the transmitter 3 and the adaptive digital filter 5 through the input terminal 1. The transmitted signal has been scrambled to eliminate correlation with a received signal. The transmitter 3 serves as an interface circuit between the subscriber terminal and the two-wire transmission line 12. The transmitter 3 comprises a unipolar/bipolar converter, a band limit filter, a buffer amplifier and the like, as needed. An outut signal from the transmitter 3 is transmitted onto the two-wire transmission line 12 through the hybrid circuit 11, and is simultaneously supplied as an echo (caused by malfunction of the hybrid circuit 11 or an impedance mismatch) to the low-pass filter 10.
A received signal which is transmitted from the local switching center is also supplied to the low-pass filter 10 through the two-wire transmission line 12 and the hybrid circuit 11. If the echo signal, the received signal, and additive noise of the received signal which occurs on the two-wire transmission line 12 are given as e(k) (where k is the time index), s(k) and n(k), respectively, an output signal u(k) from the low-pass filter 10 is given as follows: EQU u(k)=e(k)+s(k)+n(k) (1)
The principle of echo cancellation is to produce an echo replica (echo estimate) e(k) of the echo signal e(k) to cancel the echo signal. Referring to FIG. 1, the echo replica e(k) can be produced using a closed loop which comprises the adaptive digital filter 5, the D/A converter 6, the subtractor 7, the sample-and-hold circuit 8 and the A/D converter 9. Therefore, an echo-cancelled (sampled) signal r(k) can be obtained as the output signal from the sample-and-hold circuit 8 as follows: EQU r(k)=e(k)-e(k)+s(k)+n(k) (2)
where the echo replica e(k) is the output signal from the D/A converter 6 and is supplied to the subtractor 7. In equation (2), a term {e(k)-e(k)} is called a residual echo. The receiver 4 comprises a bipolar/unipolar converter, a Nyquist filter, a line equalizer, a buffer amplifier and the like, as needed.
FIG. 2 is a detailed block diagram of the adaptive digital filter 5 shown in FIG. 1. Reference numerals 50 and 51 denote input terminals; 52.sub.0, 52.sub.1, . . . , and 52.sub.N-2, delay elements; 53.sub.0, 53.sub.1, . . . , and 53.sub.N-1, coefficient generators; 54.sub.0, 54.sub.1, . . . , and 54.sub.N-1, multipliers; 55, an adder; and 56, an output terminal. Referring to FIG. 2, an input signal a(k) supplied to the input terminal 50, an input error signal r'(k) supplied to the input terminal 51, and an output signal e'(k) appearing at the output terminal 56 correspond to the input and output signals a(k), r'(k) and e'(k) of the adaptive digital filter 5 shown in FIG. 1, respectively. The input signal a(k) is simultaneously supplied from the input terminal 50 to the delay element 52.sub.0, the multiplier 54.sub.0 and the coefficient generator 53.sub.0. The delay elements 52.sub.0, 52.sub.1, . . . , and 52.sub.N-2 are connected in series with each other in the order named. The connecting points between adjacent delay elements are illustrated in FIG. 2 as a(k), a(k-1) etc. An output signal a(k-n+1) is simultaneously supplied from the delay element 52.sub.m to the delay element 52.sub.m+1, the multiplier 54.sub.m+1, and the coefficient generator 53.sub.m+1 (where m is a natural number). The input error signal r'(k) is simultaneously supplied from the input terminal 51 to the coefficient generators 53.sub.0, 53.sub.1, . . . , and 53.sub.N-1. The coefficient generator 53.sub.m receives the input signal r'(k) and the signal a(k-m) and supplies a coefficient signal C.sub.m (k) to the multiplier 54.sub.m. The N output signals from the N multipliers 54.sub.0, 54.sub.1, . . . , and 54.sub.N-1 are added together by the adder 55. The adder 55 produces the signal e'(k) which then appears at the output terminal 56. In this manner, the echo replica e'(k) can be produced on the basis of the value of the error signal r'(k). The delay time of each of the delay elements 52.sub.0, 52.sub.1, . . . , and 52.sub.N-2 is the same as the data transmission rate (T seconds). In practice, the delay elements may comprise flip-flops. The coefficient generator A.sub.m updates the coefficient data such that the error signal r'(k) is minimized in accordance with an adaptive algorithm such as linear LMS (least mean square) algorithms. The circuit arrangement shown in FIG. 2 fundamentally corresponds to that of a transversal filter. When the coefficients converge, they respectively correspond to signals obtained by approximation of the impulse response of an echo path constituting the transmitter, the hybrid circuit 11, and the low-pass filter 10.
The problems of the echo canceler shown in FIG. 1 will be descibed. If a nonlinear circuit element is present in the closed loop which comprises the adaptive digital filter 5, the D/A converter 6, the subtractor 7, the sample-and-hold circuit 8 and the A/D converter 9, the coefficients tend not to converge, and the level of the residual echo signal {e(k)-e(k)} is increased, thus increasing the noise component. In particular, the nonlinearity of the D/A converter 6 greatly degrades the signal-to-noise ratio. The possible nonlinear components from the D/A converter 6 may be classified into a quantizing noise component and a noise component inherent to the converter. The quantizing noise component can be neglected by sufficiently increasing the number of bits of the D/A converter. However, the inherent noise component can be only slightly reduced by circuit control and, even so, this results in a time-consuming manufacturing process and high cost. More particularly, in order to control the converter, fine adjustment by laser trimming must be performed. Alternatively, a nonlinearity compensation circuit must be arranged, resulting in high cost and large-scale construction.
Further, since the echo canceler is applied to a subscriber access system in a communication network, the D/A converter is required to have 12-input bit number as described above in consideration of line loss. However the circuit scale of the converter increases exponentially with the input bit number thereof, and from this point of view input bit number of the D/A converter must be small.